As geometries of the electronic devices shrink, lithography and patterning at advanced process node for planar and non-planar designs become more challenging. Generally, a gate-all-around transistor refers to the transistor having the gate material that surrounds the channel region on all sides. A vertical channel transistor is an example of the gate-all-around transistor. A vertical channel transistor is a promising candidate for semiconductor device architecture, as the gate all around structure provides improved gate control on the channel. The gate-all-around transistors can be built around nanowires, for example, silicon nanowires and InGaAs nanowires.
To maximize the gate control, an individual nanowire of the vertical transistor typically has smaller diameter than the gate length. Therefore, vertical channel transistors and integrated circuits need finer patterning process compared to horizontal channel devices.
The lithography becomes even more complicated and sophisticated on vertical channel devices due to their finer patterning requirement. This causes significant design rule limitation on patterns which can be printed, and leads to high manufacturing cost.